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1/38 june 2004 m29w400dt m29w400db 4 mbit (512kb x8 or 256kb x16, boot block) 3v supply flash memory features summary supply voltage ?v cc = 2.7v to 3.6v for program, erase and read access time: 45, 55, 70ns programming time ? 10s per byte/word typical 11 memory blocks ? 1 boot block (top or bottom location) ? 2 parameter and 8 main blocks program/erase controller ? embedded byte/word program algorithms erase suspend and resume modes ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming temporary block unprotection mode low power consumption ? standby and automatic standby 100,000 program/erase cycles per block electronic signature ? manufacturer code: 0020h ? top device code m29w400dt: 00eeh ? bottom device code m29w400d: 00efh packages ? compliant with lead-free soldering processes ? lead-free versions figure 1. packages tfbga48 (za) 6 x 9mm fbga so44 (m) tfbga48 (ze) 6 x 8mm tsop48 (n) 12 x 20mm fbga
m29w400dt, m29w400db 2/38 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. so connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. block addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. block addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a0-a17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 data input/output or address input (dq15a-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 reset/block temporary unprotect (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ready/busy output (rb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 byte/word organization select (byte ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 vss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 block protection and blocks unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. bus operations, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 unlock bypass command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/38 m29w400dt, m29w400db unlock bypass program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 unlock bypass reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 block protect and chip unprotect commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . 15 table 5. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. commands, 8-bit mode, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. data polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. data toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11.ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12.read mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 13.write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14.write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15.reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16.so44 - 44 lead plastic small outline, 525 mils body width, package outline . . . . . . . . 26 table 16. so44 ? 44 lead plastic small outline, 525 mils body width, package mechanical data 26 figure 17.tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline. . . . . . . . . 27 table 17. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . 27 figure 18.tfbga48 6x9mm ? 6x8 ball array ? 0.80mm pitch, bottom view package outline . . . . 28 table 18. tfbga48 6x9mm ? 6x8 active ball array ? 0.80mm pitch, package mechanical data. . 28
m29w400dt, m29w400db 4/38 figure 19.tfbga48 6x8mm ? 6x8 ball array ? 0.80mm pitch, bottom view package outline . . . . 29 table 19. tfbga48 6x8mm ? 6x8 active ball array ? 0.80mm pitch, package mechanical data. . 29 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 appendix a.block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. top boot block addresses m29w400dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. bottom boot block addresses m29w400d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 appendix b.block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20.programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21.programmer equipment chip unprotect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 22.in-system equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 23.in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5/38 m29w400dt, m29w400db summary description the m29w400d is a 4 mbit (512kb x8 or 256kb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are writ- ten to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the blocks in the memory are asymmetrically ar- ranged, see figures 6 and 7 , block addresses. the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the microprocessor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the ap- plication may be stored. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in so44, tsop48 (12 x 20mm), tfbga48 0.8mm pitch (6 x 9mm and 6 x8mm) packages. the memory is supplied with all the bits erased (set to ?1?). in addition to the standard versions, the packages are also available in lead-free versions, in compli- ance with jedec std j-std-020b, the st eco- pack 7191395 specification, and the rohs (restriction of hazardous substances) directive. all packages are compliant with lead-free solder- ing processes. figure 2. logic diagram table 1. signal names a0-a17 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a?1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v ss ground nc not connected internally ai06853 18 a0-a17 w dq0-dq14 v cc m29w400dt m29w400db e v ss 15 g rp dq15a?1 byte rb
m29w400dt, m29w400db 6/38 figure 3. so connections note: 1. nc = not connected figure 4. tsop connections note: 1. nc = not connected g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a?1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w rb a4 rp a7 ai06855 m29w400dt m29w400db 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 nc dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a?1 v cc dq4 dq5 a7 dq7 nc nc ai06854 m29w400dt m29w400db 12 1 13 24 25 36 37 48 dq8 nc nc a1 nc a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss
7/38 m29w400dt, m29w400db figure 5. tfbga connections (top view through package) note: 1. nc = not connected ai06856 b a 4 3 2 1 g f h dq15 a?1 a7 a3 dq10 dq8 e dq13 dq11 dq9 g v ss dq6 dq1 v ss dq14 a12 nc a17 a4 a14 a10 nc nc a6 a2 rp a8 dq4 dq3 v cc dq12 a9 byte a15 a11 nc a1 a16 dq7 dq5 dq2 a0 nc dq0 a5 e d c rb w a13 6 5
m29w400dt, m29w400db 8/38 figure 6. block addresses (x8) note: also see appendix a , tables 21 and 22 for a full listing of the block addresses. ai06857 16 kbyte 7ffffh 7c000h 64 kbyte 1ffffh 10000h 64 kbyte 0ffffh 00000h m29w400dt top boot block addresses (x8) 32 kbyte 77fffh 70000h 64 kbyte 60000h 6ffffh total of 7 64 kbyte blocks 16 kbyte 7ffffh 70000h 64 kbyte 64 kbyte 03fffh 00000h m29w400db bottom boot block addresses (x8) 32 kbyte 6ffffh 1ffffh 64 kbyte 60000h 10000h total of 7 64 kbyte blocks 0ffffh 08000h 8 kbyte 8 kbyte 7bfffh 7a000h 79fffh 78000h 8 kbyte 8 kbyte 07fffh 06000h 05fffh 04000h
9/38 m29w400dt, m29w400db figure 7. block addresses (x16) note: also see appendix a , tables 21 and 22 for a full listing of the block addresses. ai06858 8 kword 3ffffh 3e000h 32 kword 0ffffh 08000h 32 kword 07fffh 00000h m29w400dt top boot block addresses (x16) 16 kword 3bfffh 38000h 32 kword 30000h 37fffh total of 7 32 kword blocks 8 kword 3ffffh 38000h 32 kword 32 kword 01fffh 00000h m29w400db bottom boot block addresses (x16) 16 kword 37fffh 0ffffh 32 kword 30000h 08000h total of 7 32 kword blocks 07fffh 04000h 4 kword 4 kword 3dfffh 3d000h 3cfffh 3c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h
m29w400dt, m29w400db 10/38 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a17). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the program/erase con- troller. data inputs/outputs (dq0-dq7). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the program/ erase controller. data inputs/outputs (dq8-dq14). the data in- puts/outputs output the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15a-1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the word on the other addresses, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address in- puts to include this pin when byte is low except when stated explicitly otherwise. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memory?s com- mand interface. reset/block temporary unprotect (rp ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 15 and figure 15 , reset/ temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 15 and figure 15 , reset/temporary unprotect ac characteris- tics. during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. byte/word organization select (byte ). the byte/word organization select pin is used to switch between the 8-bit and 16-bit bus modes of the memory. when byte/word organization se- lect is low, v il , the memory is in 8-bit mode, when it is high, v ih , the memory is in 16-bit mode. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, pro- gram, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v ss ground. the v ss ground is the reference for all voltage measurements.
11/38 m29w400dt, m29w400db bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see tables 2 and 3 , bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 12., read mode ac waveforms , and table 12., read ac characteristics , for de- tails of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 13 and 14 , write ac waveforms, and tables 13 and 14 , write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 11., dc characteristics . during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations. additional bus opera- tions can be performed to read the electronic sig- nature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usu- ally used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 2 and 3 , bus operations. block protection and blocks unprotection. each block can be separately protected against accidental program or erase. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. block protect and chip unprotect operations are described in appendix b .
m29w400dt, m29w400db 12/38 table 2. bus operations, byte = v il note: x = v il or v ih . table 3. bus operations, byte = v ih note: x = v il or v ih . operation e g w address inputs dq15a?1, a0-a17 data inputs/outputs dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih hi-z eeh (m29w400dt) efh (m29w400d) operation e g w address inputs a0-a17 data inputs/outputs dq15a?1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih xhi-z standby v ih xxx hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 00eeh (m29w400dt) 00efh (m29w400d)
13/38 m29w400dt, m29w400db command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. see either table 5 , or 6 , depending on the configuration that is being used, for a summary of the commands. read/reset command. the read/reset com- mand returns the memory to its read mode where it behaves like a rom or eprom, unless other- wise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. once the program or erase operation has started the read/reset command is no longer accepted. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command. the auto select com- mand is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are re- quired to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another com- mand is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29w400dt is 00eeh and for the m29w400d is 00efh. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a17 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0- dq7, otherwise 00h is output. program command. the program command can be used to program a value to one address in the memory array at a time. the command re- quires four bus write operations, the final write op- eration latches the address and data and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 4., program, erase times and program, erase endurance cy- cles . bus read operations during the program op- eration will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. unlock bypass command. the unlock bypass command is used in conjunction with the unlock bypass program command to program the memo- ry. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these com- mands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. unlock bypass program command. the un- lock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. a protected block cannot be programmed; the oper- ation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock by- pass mode. see the program command for details on the behavior.
m29w400dt, m29w400db 14/38 unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode. chip erase command. the chip erase com- mand can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 4 . all bus read opera- tions during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to ?1?. all previous data is lost. block erase command. the block erase com- mand can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command. typical block erase times are given in table 4 . all bus read operations during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within the erase suspend latency time after the erase suspend command is issued (see table 4 for nu- merical values). once the program/erase control- ler has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the pe- riod when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the erase resume com- mand is issued. it is not possible to select any fur- ther blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. read- ing from blocks that are being erased will output the status register. it is also possible to issue the auto select and un- lock bypass commands during an erase suspend. the read/reset command must be issued to re- turn the device to read array mode before the re- sume command will be accepted. erase resume command. the erase resume command must be used to restart the program/ erase controller from erase suspend. an erase can be suspended and resumed more than once.
15/38 m29w400dt, m29w400db block protect and chip unprotect commands. each block can be separately protected against accidental program or erase. the whole chip can be unprotected to allow the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix b . table 4. program, erase times and program, erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. 4. maximum value measured at worst case conditions for both temperature and v cc . parameter min typ (1,2) max (2) unit chip erase (all bits in the memory set to ?0?) 2.5 s chip erase 6 35 (3) s block erase (64 kbytes) 0.8 6 (4) s program (byte or word) 10 200 (3) s chip program (byte by byte) 5.5 30 (3) s chip program (word by word) 2.8 15 (3) s erase suspend latency time 18 25 (4) s program/erase cycles (per block) 100,000 cycles data retention 20 years
m29w400dt, m29w400db 16/38 table 5. commands, 16-bit mode, byte = v ih note: x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal . the command interface only uses a-1; a0-a10 and dq0-dq7 to veri fy the commands; a11-a17, dq8-dq14 and dq15 are don't care. dq15a-1 is a-1 when byte is v il or dq15 when byte is v ih . table 6. commands, 8-bit mode, byte = v il note: x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal . the command interface only uses a-1; a0-a10 and dq0-dq7 to veri fy the commands; a11-a17, dq8-dq14 and dq15 are don't care. dq15a-1 is a-1 when byte is v il or dq15 when byte is v ih . command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30
17/38 m29w400dt, m29w400db status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 7., status register bits . data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts ?0?, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 8., data polling flowchart , gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. if any attempt is made to erase a protected block, the operation is aborted, no error is signalled and dq6 toggles for approximately 100s. if any at- tempt is made to program a protected block or a suspended block, the operation is aborted, no er- ror is signalled and dq6 toggles for approximately 1s. figure 9., data toggle flowchart , gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that ad- dress will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1? erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing, the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly.
m29w400dt, m29w400db 18/38 table 7. status register bits note: unspecified data bits should be ignored. figure 8. data polling flowchart figure 9. data toggle flowchart operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 to g g l e 0 ? ? 0 program during erase suspend any address dq7 to g g l e 0 ? ? 0 program error any address dq7 to g g l e 1 ? ? 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 ? toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai01370c dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
19/38 m29w400dt, m29w400db maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 8. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assermbly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. minimum voltage may undershoot to ?2v during trans ition and for less than 20ns during transitions. 3. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. symbol parameter min max unit t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c t lead lead temperature during soldering (1) c v io input or output voltage (2,3) ?0.6 v cc +0.6 v v cc supply voltage ?0.6 4 v v id identification voltage ?0.6 13.5 v
m29w400dt, m29w400db 20/38 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 9., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 9. operating and ac measurement conditions figure 10. ac measurement i/o waveform figure 11. ac measurement load circuit table 10. device capacitance note: sampled only, not 100% tested. parameter m29w400d unit 45 55 70 minmaxminmaxminmax v cc supply voltage 3.03.62.73.62.73.6 v ambient operating temperature (range 6) ?40 85 ?40 85 ?40 85 c ambient operating temperature (range 1) 0 70 0 70 0 70 load capacitance (c l ) 30 30 100 pf input rise and fall times 10 10 10 ns input pulse voltages 0 to v cc 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v cc /2 v ai04498 v cc 0v v cc /2 ai04499 c l c l includes jig capacitance device under test 25k ? v cc 25k ? v cc 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
21/38 m29w400dt, m29w400db table 11. dc characteristics note: 1. sampled only, not 100% tested. figure 12. read mode ac waveforms symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 (1) supply current (program/erase) program/erase controller active 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ?100 a v cc ?0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko program/erase lockout supply voltage 1.8 2.3 v ai02907 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a17/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29w400dt, m29w400db 22/38 table 12. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29w400d unit 45 55 70 t avav t rc address valid to next address valid e = v il , g = v il min455570 ns t avqv t acc address valid to output valid e = v il , g = v il max455570 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 0 ns t elqv t ce chip enable low to output valid g = v il max455570 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 0 ns t glqv t oe output enable low to output valid e = v il max253035 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max202530 ns t ghqz (1) t df output enable high to output hi-z e = v il max202530 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 5 ns t blqz t flqz byte low to output hi-z max 25 25 30 ns t bhqv t fhqv byte high to output valid max 30 30 40 ns
23/38 m29w400dt, m29w400db figure 13. write ac waveforms, write enable controlled table 13. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29w400d unit 45 55 70 t avav t wc address valid to next address valid min 45 55 70 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t wlwh t wp write enable low to write enable high min 30 30 30 ns t dvwh t ds input valid to write enable high min 25 30 45 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whwl t wph write enable high to write enable low min 30 30 30 ns t avwl t as address valid to write enable low min 0 0 0 ns t wlax t ah write enable low to address transition min 40 45 45 ns t ghwl output enable high to write enable low min 0 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 30 35 ns t vchel t vcs v cc high to chip enable low min 505050 s ai01869c e g w a0-a17/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
m29w400dt, m29w400db 24/38 figure 14. write ac waveforms, chip enable controlled table 14. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29w400d unit 45 55 70 t avav t wc address valid to next address valid min 45 55 70 ns t wlel t ws write enable low to chip enable low min 0 0 0 ns t eleh t cp chip enable low to chip enable high min 30 30 30 ns t dveh t ds input valid to chip enable high min 25 30 45 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 30 ns t avel t as address valid to chip enable low min 0 0 0 ns t elax t ah chip enable low to address transition min 40 45 45 ns t ghel output enable high chip enable low min 0 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 30 35 ns t vchwl t vcs v cc high to write enable low min 505050 s ai01870c e g w a0-a17/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
25/38 m29w400dt, m29w400db figure 15. reset/block temporary unprotect ac waveforms table 15. reset/block temporary unprotect ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter m29w400d unit 45 55 70 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min000 ns t plpx t rp rp pulse width min 500 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 10 s t phphh (1) t vidr rp rise time to v id min 500 500 500 ns ai02931 rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
m29w400dt, m29w400db 26/38 package mechanical figure 16. so44 - 44 lead plastic small outline, 525 mils body width, package outline note: drawing is not to scale. table 16. so44 ? 44 lead plastic small outline, 525 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.80 0.1102 a1 0.10 0.0039 a2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 c 0.15 0.10 0.20 0.0059 0.0039 0.0079 cp 0.08 0.0030 d 28.20 28.00 28.40 1.1102 1.1024 1.1181 e 13.30 13.20 13.50 0.5236 0.5197 0.5315 eh 16.00 15.75 16.25 0.6299 0.6201 0.6398 e 1.27 ? ? 0.0500 ? ? l 0.80 0.0315 a8 8 n44 44 so-d e n d c l a1 eh a 1 e cp b a2
27/38 m29w400dt, m29w400db figure 17. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 17. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 305305 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
m29w400dt, m29w400db 28/38 figure 18. tfbga48 6x9mm ? 6x8 ball array ? 0.80mm pitch, bottom view package outline note: drawing is not to scale. table 18. tfbga48 6x9mm ? 6x8 active ball array ? 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 4.000 ? ? 0.1575 ? ? ddd 0.100 0.0039 e 9.000 8.900 9.100 0.3543 0.3504 0.3583 e 0.800 ? ? 0.0315 ? ? e1 5.600 ? ? 0.2205 ? ? fd 1.000 ? ? 0.0394 ? ? fe 1.700 ? ? 0.0669 ? ? sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ? e1 e d1 d e b a2 a1 a bga-z00 ddd fd fe sd se e ball "a1"
29/38 m29w400dt, m29w400db figure 19. tfbga48 6x8mm ? 6x8 ball array ? 0.80mm pitch, bottom view package outline note: drawing is not to scale. table 19. tfbga48 6x8mm ? 6x8 active ball array ? 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 4.000 ? ? 0.1575 ? ? ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.600 ? ? 0.2205 ? ? e 0.800 ? ? 0.0315 ? ? fd 1.000 ? ? 0.0394 ? ? fe 1.200 ? ? 0.0472 ? ? sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ? e1 e d1 d eb a2 a1 a bga-z32 ddd fd fe sd se e ball "a1"
m29w400dt, m29w400db 30/38 part numbering table 20. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example:m29w400d 55 n 6 t device type m29 operating voltage w = v cc = 2.7 to 3.6v device function 400d = 4 mbit (512kx8 or 256kx16), boot block array matrix t = top boot b = bottom boot speed 45 = 45ns 55 = 55ns 70 = 70ns package m = so44 n = tsop48: 12 x 20mm za = tfbga48: 6 x 9mm ze = tfbga48: 6 x 8mm temperature range 6 = ?40 to 85 c 1 = 0 to 70 c option blank = standard packing t = tape & reel packing e = lead-free and rohs package, standard packing f = lead-free and rohs package, tape & reel packing
31/38 m29w400dt, m29w400db appendix a. block address table table 21. top boot block addresses m29w400dt table 22. bottom boot block addresses m29w400d # size (kbytes) address range (x8) address range (x16) 10 16 7c000h-7ffffh 3e000h-3ffffh 9 8 7a000h-7bfffh 3d000h-3dfffh 8 8 78000h-79fffh 3c000h-3cfffh 7 32 70000h-77fffh 38000h-3bfffh 6 64 60000h-6ffffh 30000h-37fffh 5 64 50000h-5ffffh 28000h-2ffffh 4 64 40000h-4ffffh 20000h-27fffh 3 64 30000h-3ffffh 18000h-1ffffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh # size (kbytes) address range (x8) address range (x16) 10 64 70000h-7ffffh 38000h-3ffffh 9 64 60000h-6ffffh 30000h-37fffh 8 64 50000h-5ffffh 28000h-2ffffh 7 64 40000h-4ffffh 20000h-27fffh 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
m29w400dt, m29w400db 32/38 appendix b. block protection block protection can be used to prevent any oper- ation from modifying the data stored in the flash. each block can be protected individually. once protected, program and erase operations on the block fail to change the data. there are three techniques that can be used to control block protection, these are the program- mer technique, the in-system technique and tem- porary unprotection. temporary unprotection is controlled by the reset/block temporary unpro- tection pin, rp ; this is described in the signal de- scriptions section. unlike the command interface of the program/ erase controller, the techniques for protecting and unprotecting blocks change between different flash memory suppliers. for example, the tech- niques for amd parts will not work on stmicro- electronics parts. care should be taken when changing drivers for one part to work on another. programmer technique the programmer technique uses high (v id ) volt- age levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a block follow the flowchart in figure 20., programmer equipment block protect flow- chart .to unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. to unprotect the chip follow figure 21., programmer equipment chip unprotect flowchart . table 23., programmer technique bus operations, byte = v ih or v il , gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the micro- processor bus, therefore this technique is suitable for use after the flash has been fitted to the sys- tem. to protect a block follow the flowchart in figure 22., in-system equipment block protect flow- chart . to unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. to unprotect the chip follow figure 23., in-system equipment chip unprotect flowchart . the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro- cedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. table 23. programmer technique bus operations, byte = v ih or v il operation e g w address inputs a0-a17 data inputs/outputs dq15a?1, dq14-dq0 block protect v il v id v il pulse a9 = v id , a12-a17 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9 = v id , a12-a17 block address others = x pass = xx01h retry = xx00h block unprotection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v ih , a9 = v id , a12-a17 block address others = x retry = xx01h pass = xx00h
33/38 m29w400dt, m29w400db figure 20. programmer equipment block protect flowchart address = block address ai03469 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
m29w400dt, m29w400db 34/38 figure 21. programmer equipment chip unprotect flowchart protect all blocks ai03470 a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current block address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current block n = 0 current block = 0 wait 4s w = v il ++n = 1000 start yes yes no no last block yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
35/38 m29w400dt, m29w400db figure 22. in-system equipment block protect flowchart ai03471 write 60h address = block address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = block address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = block address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = block address a0 = v il , a1 = v ih , a6 = v il
m29w400dt, m29w400db 36/38 figure 23. in-system equipment chip unprotect flowchart ai03472 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current block = 0 wait 10ms write 40h address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all blocks increment current block last block yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
37/38 m29w400dt, m29w400db revision history table 24. document revision history date version revision details 26-jul-2002 -01 first issue 19-feb-2003 2.0 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). revision history moved to end of document. typical after 100k w/e cycles column removed from table 4 , program, erase times and program, erase endurance cycles , data retention and erase suspend latency time parameters added. common flash interface removed from datasheet. lead-free package options e and f added to table 20., ordering information scheme . document promoted from product preview to preliminary data status. 28-may-2003 2.1 t wlwh and t eleh parameters modified for all speed classes in tables 13 and 14 , respectively (? write ac characteristics, write enable controlled ? and ? write ac characteristics, chip enable controlled ?). minor text changes. tsop48 package updated (figure 17 and table 17 ). 30-sep-2003 2.2 document status changed to full datasheet. tfbga48 6x8 package added. tlead parameter added in table 8., absolute maximum ratings . 6-oct-2003 2.3 t glqv modified in table 12, read ac characteristics. 16-jan-2004 3.0 rb pin description corrected in table 1., signal names . 8-jun-2004 4.0 tape and reel option updated in table 20., ordering information scheme . lead-free packaging promotion updated in features summary , summary description , maximum rating and part numbering sections.
m29w400dt, m29w400db 38/38 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack ? is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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